Process for fabricating interconnect networks

ABSTRACT

The process includes depositing a filling material in trenches formed in at least one layer of dielectric so as to fill open pores in the dielectric. The filling material is intended to prevent the subsequent diffusion of the interconnect metal and/or of a metal of a diffusion barrier, and may be non-porous. The filling material preferably has a low dielectric constant.

FIELD OF THE INVENTION

The present invention relates to interconnect networks for integratedcircuits, and more particularly to copper interconnects formed by thedamascene process.

BACKGROUND OF THE INVENTION

Interconnect structures for integrated circuits are conventionally madeof aluminum doped with between 2 and 4% copper. In this case, theprocess includes depositing the metal, then etching it to form theinterconnect network and finally deposit on top of it the dielectricwhich will serve both as lateral insulation of the lines and as verticalinsulation of the metal levels. To improve the performance of thecircuits, especially in terms of speed and consumption, copperinterconnects are used. This is because, with the low resistively ofcopper, which is almost half that of copper-doped aluminum, suchinterconnects allow the resistances R_(int) to be reduced. A drawbackwith this approach is that copper is very difficult to etch.

A process, known as the damascene process, has therefore been developedand has replaced the etching of the metal. According to the damasceneprocess, as described in Patent Application FR 2 794 286, trenches arefirstly etched in a generally porous dielectric of low dielectricconstant, then a diffusion barrier, made of a metal or a metal nitride(for example Ta, Ti, TiN, TaN), is deposited as a layer lining the wallsof these trenches and then the interconnect metal is deposited in thetrenches. Finally, the copper on the surface of the dielectric is“planed” by chemical-mechanical polishing (CMP) so as to leave metalonly in the trenches.

However, during deposition of the metal barriers and then of the metalin the trenches etched in the dielectric, the metal may diffuse into theopen pores thereof to a greater or lesser depth. Thus, there is a rapidchange in the nature of the material, which then loses its insulatingfunction. Furthermore, because of electronic component miniaturization,the metal lines are coming closer and closer together, being separatedby a mean distance of the order of 0.1 μm. These small dimensions andthe degradation of the dielectric mean that there is a risk of formingshort circuits and of degrading the lateral capacitance between twometal lines. Such manifestations impair the proper performance of theelectronic components produced.

Thus, it has been envisaged, as described in the Texas Instrumentsdocument “MRS Proc. Vol. 511, p. 213” to plug the open pores of thedielectric material using a layer of silicon oxide. However, with aconventional silicon oxide deposited by PECVD (Plasma Enhanced ChemicalVapour Deposition), the metal cannot be deposited properly because ofthe inhomogeneity of the silica layer. Another drawback associated withdepositing an oxide layer is the degradation of the lateral capacitancebetween two metal lines, resulting in a stray capacitance, because ofthe high dielectric constant of the oxide (which is about 4).

SUMMARY OF THE INVENTION

The present invention provides a process for fabricating an interconnectnetwork which overcomes these drawbacks.

In particular, the present invention provides a process for fabricatingan interconnect network which reduces the diffusion of metal into theopen pores of the dielectric, thus making it possible to reduce theformation of short circuits and of induced effects of one line of thenetwork on another.

The invention provides a process for fabricating an interconnectnetwork, comprising the deposition of an interconnect metal,characterized in that, prior to the deposition of the interconnectmetal, a filling material is deposited in trenches formed in at leastone layer of dielectric so as to fill open pores in the dielectric. Thefilling material is intended to prevent the subsequent diffusion of theinterconnect metal and/or of a metal of a diffusion barrier, and may benon-porous. The filling material preferably has a low dielectricconstant. The term “material having a low dielectric constant” isunderstood to mean a material whose dielectric constant is less than 4.

The process may also include deposition of the filling material,deposition of a diffusion barrier in the trenches, and deposition of theinterconnect material. The trenches may be formed in at least one layerof dielectric. Preferably, the trenches are formed in two layers ofdielectric.

The process is particularly suitable for the production of doubledamascene structures. The process may thus comprise the followingsuccessive steps: formation of a first layer of dielectric; depositionof a stop layer on the first layer of dielectric; etching of the firstlayer of dielectric in order to form a trench; deposition of a secondlayer of dielectric; etching of the second layer of dielectric;deposition of a filling material so as to fill the open pores in the twolayers of dielectric; removal of the filling material, except in theopen pores in the two layers of dielectric, this step being optional;deposition of a diffusion barrier; and deposition of an interconnectmetal. The filling material may be removed, except from the open poresin the dielectric. The filling material may be a polymer.

According to a preferred method of implementing the process of theinvention, the polymer is an aromatic polymer, for example of thepolyarylether type, or else a thermally stable aromatic polymer. Theinterconnect metal may comprise copper.

The non-porous filling material preferably has a decompositiontemperature or melting point above 450° C. Its dielectric constant maybe less than 4, and is preferably between 2.5 and 3.5. Moreparticularly, a polymer will be chosen whose dielectric constant isbetween 2.6 and 2.8. Furthermore, the filling material according to theinvention may have a high filling capacity. Thus, in particular, it maybe capable of filling pores less than 100 nm, preferably less than 20 nmand even more preferably less than 10 nm in size.

The filling material may be deposited in various conventional ways. Itmay be envisaged to deposit it by CVD (Chemical Vapor Deposition) or byspin-on coating. However, according to one particularly advantageousvariant of the process of the invention, the filling material is indispersed form and deposited by spin-on coating. In a preferredembodiment, the material deposited is then crosslinked. The fillingmaterial may then be removed from the trenches. It may be envisaged toremove it using a directional anisotropic oxidizing plasma, thus leavingthe pores in the low-dielectric-constant porous material plugged.

According to a preferred method of implementing the process of theinvention, the structure obtained at this stage in the process issubjected to a cleaning step, for example by spraying or by dipping. Theprocess of the invention is then continued conventionally, by depositinga diffusion barrier and an interconnect metal. Preferably, theinterconnect metal comprises copper.

The invention also relates to a semiconductor device comprising aninterconnect network comprising at least one layer of dielectric and atleast one interconnect line or at least one interconnect via formed in atrench, characterized in that, since the dielectric has open pores, thedevice includes a material for filling said open pores, the fillingmaterial being placed between the dielectric and the interconnect linesor vias. Preferably, the filling material is located in the open poresin the dielectric, that is to say the open pores in the walls of thetrench. The filling material may have the characteristics describedabove.

The semiconductor device may especially have a double damascenestructure. In this case, the device comprises two layers of dielectric.The device may thus comprise: two layers of dielectric; a fillingmaterial for filling the open pores in the walls of a trench formed inthe two layers of dielectric, said filling material being located insaid open pores; and a diffusion barrier and/or an interconnect metal,filling the trench. Preferably, the interconnect network is based oncopper.

The process according to the invention is very suitable for theproduction of interconnects with a single damascene or double damascenestructure having several metal levels. Further advantages andcharacteristics of the invention will become apparent on examining thedetailed description of an entirely nonlimiting method of implementingthe process of the invention.

BRIEF DESCRIPTION OF THE DRAWINGS

The rest of the description refers to FIGS. 1 to 4 and to the main stepsof the process for fabricating an interconnect network with a doubledamascene structure having one metal level according to this method ofimplementing the process of the invention.

FIGS. 1 to 4 are cross sections through the interconnect device,illustrating the various steps of the fabrication process of theinvention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

FIG. 1 shows a metal contact pad 1 on a wafer. The metal used is astandard interconnect metal, such as copper, aluminum or tungsten.However, the process of the invention is particularly suitable for theproduction of interconnects comprising copper. Deposited successively onthis metal contact pad 1 are a barrier layer 2 and a layer 3 of adielectric called ILD (Inter-Layer Dielectric). The barrier layer 2 may,for example, be an inorganic dielectric.

Next, a stop layer 4 is deposited on the layer 3 and then the layer 3 isetched to produce trenches 6. The trenches 6 have walls 6 a and 6 bwhich are generally perpendicular to the upper surface of the stop layer4. A layer 5 of dielectric called IMD (Inter-Metal Dielectric) is thendeposited. This deposition is followed by etching of the layers 3 and 5,for example by dry fluorine etching.

In the double damascene process, the same low-dielectric-constantdielectric is generally used to produce the layers 3 and 5. Theexpression “low-dielectric-constant dielectric” is understood to mean amaterial whose dielectric constant is less than 4. The material may beporous, or even mesoporous with a mean pore size of less than 10 nm, oreven of between 3 and 6 nm, with a distribution ranging between 1 and 20nm.

This dielectric may be an inorganic, organic or hybrid dielectric.Examples include porous methyl silesquioxane, a xerogel or otherinorganic materials having a porous structure. A xerogel whosedielectric constant is about 2 will be preferred. Next, prior todepositing a diffusion barrier 9, a filling material 8 is deposited onthe layer 5 and on the walls 6 a and 6 b of the trenches 6 (see FIG. 2).This is because it turns out that the walls 6 a and 6 b of the trenches6 have a certain number of open pores 7, which the filling material 8 iscapable of filling.

According to an embodiment of the invention, the filling material 8 isthermally stable. Its decomposition temperature or melting point ispreferably above 450° C., especially so as to be able to withstand thepossible annealing operations during fabrication of the electroniccomponents. The filling material 8 must be non-porous, although it canhave a certain free volume so as to obtain a low dielectric constant.The term “non-porous” is understood to mean that its porosity preventsthe interconnect metal and/or the metal of the metal barrier fromdiffusing into the open pores in the dielectric.

The filling material 8 preferably has a low dielectric constant so as toavoid excessively strong interactions between the metal lines of thenetwork which are often separated by only approximately 0.1 μm. Forexample, filling materials 8 having a dielectric constant of less than4, and preferably between 2.5 and 3.5, are used. More particularly, afilling material 8 having a dielectric constant of between 2.6 and 2.8will be chosen. Apart from these characteristics, the filling material 8may also have a high filling capacity, so as to be able to fill the openpores 7, having a size of very much less than 100 nm, in the layers 3and 5 of the dielectric. The size of the pores in the dielectrics usedmay in fact be as low as 20 nm, or even 10 nm.

Moreover, it is preferable for the filling material 8 to be compatiblewith the subsequent deposition of a diffusion barrier 9, that is to saythat it is desirable for there to be no degradation induced by thedeposition of the diffusion barrier 9 by PVD (Physical Vapor Deposition)or CVD (Chemical Vapor Deposition). Furthermore, because the diffusionbarrier 9 may be deposited by CVD it is preferable for the fillingmaterial 8 to be chemically stable. The filling material 8 may beorganic, inorganic or hybrid.

As particularly preferred filling materials, mention may be made ofaromatic polymers, possibly thermally stable ones. Thus, use may be madeof the polymer called SILK (sold by Dow Chemical) or of the polymercalled FLARE (sold by Honeywell), which are aromatic non-porous polymershaving a dielectric constant of about 2.7. The filling material 8 may bedeposited in various ways. For example it may be envisaged to deposit itby CVD or by spin-on coating.

However, it is preferred, when this is possible, to deposit the fillingmaterial 8 by spin-on coating, especially when it is a polymer. This isbecause deposition by CVD takes place by growth of the filling material8 on the walls of the trenches 6. Given the dimensions of the trenches6, there would be a risk of forming a plug before the filling material 8has been able to fill the open pores 7 in the layers 3 and 5 of thedielectric. This risk is avoided by spin-on deposition.

If the filling material 8 is deposited by spin-on coating, the materialis in the form of a phase dispersion. A drop of the filling material 8is then deposited on the device. Owing to the spinning, this dropspreads out and runs into the trenches 6 and then fills the open pores 7in the layers 3 and 5 of the dielectric. This step is carried out for atime long enough to fill the entire open porous structure of the layers3 and 5 of dielectric.

Once the filling material 8 has been deposited by spin-on coating it isthen crosslinked so as to make it stable. The crosslinking may becarried out by various methods. It is possible to envisage a heattreatment at a temperature of about 400° C., or at a lower temperature.Care should then be taken not to exceed the decomposition temperature ormelting point of the filling material 8. It is also possible to envisagecrosslinking by treatment with UV radiation or else with an electronbeam.

The filling material 8 is then removed from the surface of the damascenestructure, except from the open pores 7 in the layers 3 and 5 ofdielectric. This removal may be carried out by anisotropic etching usingan oxidizing plasma. FIG. 3 shows the damascene structure at this stagein the process, the open pores 7 in the layers 3 and 5 of dielectricbeing filled with the crosslinked filling material 8.

The step of etching the filling material 8 may entail the metal 1 beingspattered onto the walls of the trenches 6. To remove suchcontaminations, the wafer may be subjected to a cleaning step, forexample liquid cleaning. This step also allows the traces of fillingmaterial 8 that may possibly have formed during the etching step to beremoved. To complete the process, a metal diffusion barrier 9 and thenan interconnect metal 10 are deposited in the trenches 6 of thesemiconductor device (see FIG. 4).

The process has an additional advantage. Conventionally, duringrecrystallization of the metal, the grains of the metal grow laterallyand may degrade the structure. The association between the fillingmaterial 8 and the dielectric has the advantage of laterallyconsolidating this structure, making it less friable. Next, the excessinterconnect metal 10 is removed from the surface of the layer 5 ofdielectric by chemical-mechanical polishing.

FIG. 4 shows the semiconductor device at the end of the damasceneprocess. On top of the metal contact pad 1 there is the barrier layer 2,on top of which there is the layer 3 of dielectric. On the layer 3 thereis the stop layer 4, and on the stop layer 4 there is the layer 5 ofdielectric. The open pores 7 in the dielectric are filled with thefilling material 8. The filling material 8, The trenches 6 are filledwith the diffusion barrier 9 and the interconnect metal 10.

The semiconductor device thus produced with damascene interconnects mayadvantageously serve as a basis for the production of integratedcircuits whose performance is improved since the risk of a shortcircuit, resulting from the diffusion of metal into the layers, isreduced. Furthermore, by incorporating the low-dielectric-constantfilling material 8, the lateral capacitance between two metal lines ofthe semiconductor device is reduced. Consequently, the induced effectsof one line on another are reduced.

1. A semiconductor device comprising: an interconnect network comprisingat least one dielectric layer having a trench, and at least oneinterconnect formed in the trench, the dielectric layer having pores; afilling material filling only in the pores between the dielectric layerand the interconnect; and a diffusion barrier layer between theinterconnect and the dielectric layer, and in contact with thedielectric layer and the filling material.
 2. The semiconductor deviceaccording to claim 1 wherein the at least one dielectric layer comprisestwo dielectric layers.
 3. The semiconductor device according to claim 2wherein the filling material fills pores in the two dielectric layers.4. The semiconductor device according to claim 1 wherein theinterconnect comprises copper.
 5. The semiconductor device according toclaim 1 wherein the filling material is a polymer.
 6. The semiconductordevice according to claim 1 wherein the filling material is a thermallystable aromatic polymer.
 7. The semiconductor device according to claim1 wherein the filling material has a melting point above 450° C.
 8. Thesemiconductor device according to claim 1 wherein the filling materialhas a dielectric constant of less than four.
 9. The semiconductor deviceaccording to claim 1 wherein the filling material has a dielectricconstant preferably between 2.5 and 3.5.
 10. The semiconductor deviceaccording to claim 1 wherein the filling material has a dielectricconstant between 2.6 and 2.8.
 11. The semiconductor device according toclaim 1 wherein the filling material fills pores having a size of lessthan 100 nm.
 12. The semiconductor device according to claim 1 whereinthe filling material fills pores having a size of less than 20 nm. 13.The semiconductor device according to claim 1 wherein the fillingmaterial fills pores having a size of less than 10 nm.
 14. Asemiconductor device comprising: an interconnect network comprising adielectric layer having a trench, and an interconnect formed in thetrench, the dielectric layer having pores; a filling material only inthe pores; and a diffusion barrier layer covering and in contact withthe filled pores and the dielectric layer.
 15. The semiconductor deviceaccording to claim 14 wherein the interconnect comprises copper.
 16. Thesemiconductor device according to claim 14 wherein the filling materialcomprises a polymer.